The present invention relates to a metal oxide semiconductor (MOS) transistor and, more particularly, to a high voltage MOS transistor.
To establish an improved high voltage MOS transistor by preventing field concentration near an edge of a gate electrode, an attempt has been made in which there has been additionally provided a high resistant layer adjacent a drain as a part of the drain region, the conductivity type of the high resistant layer being the same as the drain.
FIG. 1 shows a cross-sectional view of a conventional high voltage MOS transistor. In FIG. 1, the conventional transistor comprises a P type substrate 1. an N.sup.+ type source layer 2, an N.sup.+ type drain layer 3, a P.sup.+ type layer 4, an N.sup.- type high resistant layer 5, a source electrode 6, a drain electrode 7, insulating layers 8, 8' and 8", a gate electrode 9, field plate layers 6' and 7', and an additional field plate layer 10 made of Al, polycrystalline silicon, or the like.
The P.sup.+ type layer 4 surrounds the N.sup.+ type source layer 2 for providing a gate channel for the transistor. The layer 4 is formed by a diffusion--self-alignment process. A high voltage diffusion-self-alignment MOS transistor is described in Awane et al, U.S. Pat. No. 4,058,822 issued Nov. 15, 1977, assigned to the present assignee, entitled "HIGH VOLTAGE, LOW ON-RESISTANCE DIFFUSION-SELFALIGNMENT METAL OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF". The disclosure of this patent is incorporated herein by reference.
Around the N.sup.+ type drain layer 3, the N.sup.- type high resistant layer 5 is provided for preventing field concentration at the edge of the gate electrode 9. The layer 5 constitutes a part of the drain region. Each of the source electrode 6 and the drain electrode 7 is composed by Al, polycrystalline silicon, or the like. Each of the field plate layers 6' and 7' extends from each of the source electrode 6 and the drain electrode 7. The gate electrode 9 is made of Al or polycrystalline silicon, called a silicon gate. The layer 10 is prepared simultaneously with the preparation of the silicon gate 9.
The field plate layer 6' functions to reduce field concentration at the edges of the gate electrode 9. The field plate layers 7' and 10 function to reduce field concentration in the boundary between the N.sup.+ type layer 3 and the N.sup.- type layer 5.
If one of the field plate layer 6' and the field plate layer 7' extends over a suitable limitation, a reverse field plate effect may be remarkably generated which is applied to the drain portion 3 by the layer 6' or to the edge of the gate electrode 9 by the layer 7'. This reduces the value of a sustained voltage.
To eliminate the generation of the reverse field plate effect, the above-mentioned structure of the transistor includes a region A of the N.sup.- type high resistant layer 5 uncovered with the field plate layers 6' and 7' made of Al or the polycrystalline silicon. However, inevitably the amount of a sustainable voltage in the ON condition, the amount of the drain current and the value of R.sub.ON will undesirably vary according to this structure.